文献
J-GLOBAL ID:201702241632852741
整理番号:17A0329185
ファンアウトウエハレベルパッケージング(FOWLP)のための多層PBO系Cu RDLプロセスの評価【Powered by NICT】
Evaluation on multiple layer PBO-based Cu RDL process for Fan-Out Wafer Level Packaging (FOWLP)
著者 (9件):
Boon Soh Siew
(Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 2, Fusionopolis Way, #08-02 Innovis Tower, Singapore 138634)
,
Chui K. J.
(Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 2, Fusionopolis Way, #08-02 Innovis Tower, Singapore 138634)
,
David Ho S. W.
(Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 2, Fusionopolis Way, #08-02 Innovis Tower, Singapore 138634)
,
Sek S. A.
(Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 2, Fusionopolis Way, #08-02 Innovis Tower, Singapore 138634)
,
Yu Mingbin
(Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 2, Fusionopolis Way, #08-02 Innovis Tower, Singapore 138634)
,
Lianto Prayudi
(Applied Materials, 10 Science Park Road, Singapore 117684)
,
Gu Yu
(Applied Materials, 10 Science Park Road, Singapore 117684)
,
See Guan Huei
(Applied Materials, 10 Science Park Road, Singapore 117684)
,
Bernt Marvin L.
(Applied Materials, 655 West Reserve Drive, Kalispell, MT 59901, USA)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2016
号:
EPTC
ページ:
662-665
発行年:
2016年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)