Rchr
J-GLOBAL ID：200901027626254962
Update date: Jan. 31, 2024
Onodera Hidetoshi
オノデラ ヒデトシ | Onodera Hidetoshi
Affiliation and department：
Job title：
Professor,Professor
Research field (1)：
Electronic devices and equipment
Research keywords (2)：
集積回路工学
, Integrated Circuits Technology
Research theme for competitive and other funds (38)：
- 2017 - 2020 Research on computing infrastructure aimed at realizing an IoT society to come
- 2016 - 2020 LSI Design Method for Minimum Energy Operation
- 2014 - 2017 A Study on Energy Harvesting Embedded Computers as a Social Infrastructure
- 2013 - 2017 LSI design methodology that enables robust operation under the supply as low as threshold voltage by self-compensating performance variability
- 2010 - 2012 Integrated Circuit Design for Robust Operation under Low Supply Voltage
- 2007 - 2009 Variation and Defect Aware Design of Integrated Circuits
- 2002 - 2004 Research of a High-speed Signal Transmission Scheme for Integrated Circuits
- 2001 - 2002 動き補償を利用した動画像の実時間背景・対象物分離アルゴリズムとハードウエアの開発
- 1999 - 2001 Development of a Energy-Recovering Low-Power Processor Architecture.
- 1999 - 2001 Development of Statistical Performance Analysis and Optimization Methods for Large Scale Integrated Circuits
- 1998 - 2000 Development of a Functional LSI Achieving Low-rate Multimedia Data Transmission.
- 1998 - 1999 Development of a Memory-Based Low-Energy Processor for Real-Time Motion
- 1997 - 1998 Optimization of detailed design for UDSM (ultra deep submicron) integrated circuits
- 1996 - 1997 Development of Curriculums for Education of VLSI System Design.
- 1996 - 1997 Statistical modeling method for scaled MOSFET
- 1995 - 1997 Development of a Computing System by a Functional Memory Type Parallel Processor.
- 1994 - 1995 Simultaneous Circuit and Layout Design Method for Analog LSIs under Performance Constraints
- 1994 - 1995 Development of Educational Microprocessors for Computer Science Education
- 1994 - 1995 Development of Comprehensive Set of LSI CAD Benchmarks
- 1993 - 1995 Effective Design Methodology for Analog LSIs that Acquires and Reuses Design
- 1992 - 1994 Development of a Computer Specific to LSI Geometrical Processing
- 1992 - 1993 Development of Education-Microprocessor for Computer Engineering and VLSI Engineering.
- 1990 - 1992 Studies on Functional Memory Type Parallel Processor Architectures and Their Massively Parallel Algorithms.
- 1990 - 1991 Research on High-Level Information Extraction in Integrated Circuit Design
- 1989 - 1991 Development of an Integrated Analog-Digital CAD System
- 1988 - 1990 新しい超高速変調・復調光通信システムに関する基礎研究
- 1989 - 1989 アナログ基本モジュールの設計自動化に関する研究
- 1987 - 1988 Studies on a Hierarchical CAD System for Analog LSIs
- 1987 - 1987 MOS集積化循環型高速A-D,D-A変換回路の研究
- 1985 - 1987 A Basic Study on Optical Amplification by use of Synchronization of Coupled Laser Oscillators
- 1986 - 1986 MOS集積化能動RCフィルタ回路の研究
- 1985 - 1985 MOS FET モデルパラメータの最適抽出に関する研究
- ディジタル回路設計技術
- アナログ回路設計技術
- 集積回路の計算機援用設計法
- Digital Circuit Design Technique
- Analog Circuit Design Technique
- Computer-Aided Design for Integrated Circuits
Show all
Papers (620)：
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Shoya SONODA, Jun SHIOMI, Hidetoshi ONODERA. Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2023. E106.A. 3. 542-550
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Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, et al. Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation. Japanese Journal of Applied Physics. 2022. 61. SM. SM0804-SM0804
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Misaki Udo, Mahfuzul Islam, Hidetoshi Onodera. Homogeneous Ring Oscillator with Staggered Layout for Gate-level Delay Characterization. IEEE International Conference on Microelectronic Test Structures. 2022. 2022-March
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Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera. Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. SOCC. 2022. 1-6
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Jun Shiomi, Shuya Kotsugi, Boyu Dong, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi. Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics. 2021 58th ACM/IEEE Design Automation Conference (DAC). 2021
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MISC (161)：
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RTN-induced Delay Fluctuation under Dynamic Supply and Back-gate Voltage Tuning. 2020. 2020. 65-71
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Monte Carlo-based Delay Variation Analysis with Non-Linear Circuit Delay Model. 2020. 2020. 59-64
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塩見 準, 石原 亨, 小野寺 秀俊, 新家 昭彦, 納富 雅也. 集積ナノフォトニクスに基づく近似並列乗算器を用いた低レイテンシ光ニューラルネットワーク-VLSI設計技術 ; デザインガイア2019 : VLSI設計の新しい大地. 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報. 2019. 119. 282. 127-132
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Shengyu Liu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera. A Process-Scheduler-Based Approach to Minimum Energy Point Tracking. DA Symposium 2019 (poster). 2019
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福田 展和, 塩見 準, 石原 亨, 小野寺 秀俊. 幅広い動作環境にわたってLSIの最大遅延特性を追跡するクリティカルパスレプリカの構成法-A Method of Constructing a Replica Circuit Tracking Maximum Delay Characteristics of an LSI Circuit over a Wide Range of Operating Environments-VLSI設計技術. 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報. 2018. 118. 29. 25-30
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Patents (18)：
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Indoctor
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再構成可能な遅延回路、並びにその遅延回路を用いた遅延モニタ回路、ばらつき補正回路、ばらつき測定方法及びばらつき補正方法
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直交型ソレノイドインダクタ
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ソレノイドインダクタ
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インダクタ
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Books (5)：
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VLSI Design and Test for Systems Dependability, Shojiro Asai Ed.
Springer 2018
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情報処理学会論文誌「システムLSI設計とその技術」
情報処理学会論文誌 2007
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IEICE Transactions on Fundamentals, Special Section on VLSI Design and CAD Algorithms
IEICE Transactions on Fundamentals,E89-A,12 2006
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LSI配線の解析と合成 ---ディープサブミクロン世代のLSI設計技術---
培風館 2003
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IEICE Transaction on Fundamentals
SepcialSection on CAD,Vol.E84-A,No. 11 2001
Lectures and oral presentations (35)：
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Reconfigurable Architecture for Dependability and Energy Efficiency
(International Workshop on Cross-layer Resiliency 2019)
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Minimum Energy Operation of Voltage-Scaled Circuits
(International Workshop on Cross-layer Resiliency 2018)
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Toward minimum energy operation of voltage-scaled circuits
(IEEE/ACM 10th Workshop on Variability Modeling and Characterization 2017)
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Toward minimum energy operation
(International Workshop on Cross-Layer Resiliency 2017)
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Circuit Aging - Measurement Techniques
(IEEE International Reliability Physics Symposium, Monday Tutorial 2016)
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Works (10)：
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LSI製造ばらつきモデルを内蔵した統計解析回路シミュレータの研究開発
2005 -
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Optimal Design Methodology under Substrate Biasing
2005 -
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ばらつき考慮タイミング設計手法開発
2003 - 2004
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Variation-aware Timing Analysis Techniques
2003 - 2004
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基板バイアス制御下での最適設計技術
2004 -
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Education (4)：
- - 1983 Kyoto University
- - 1983 Kyoto University Graduate School, Division of Engineering
- - 1978 Kyoto University Faculty of Engineering
- - 1978 Kyoto University Faculty of Engineering
Professional career (1)：
Committee career (2)：
- 2001 - 2002 IEEE Solid-State Circuits Society,Kansai Chapter,Chairman
- 2000 - 2001 電子情報通信学会 VLSI設計技術研究専門委員会委員長
Awards (1)：
Association Membership(s) (4)：
ACM
, IEEE
, 情報処理学会
, 電子情報通信学会
