Rchr
J-GLOBAL ID：200901051769488954
Update date: Feb. 01, 2024
Namba Kazuteru
ナンバ カズテル | Namba Kazuteru
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Affiliation and department：
Chiba University
About Chiba University
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Job title：
Chiba University
Homepage URL (2)：
http://www.icsd2.tj.chiba-u.jp
,
http://www.icsd2.tj.chiba-u.jp/research-e.htm
Research field (1)：
Computer systems
Research keywords (1)：
dependable computing
Research theme for competitive and other funds (7)：
2021 - 2024 Ultrafast Superlattice Phase-change Artificial Synapse
2019 - 2022 Improvement on High Resolution of Environmental Remote Sensed Imagery using Multi Beam Synthetic Aperture Radar
2020 - 2022 誤差許容計算における PCM 書き込み時間削減
2015 - 2017 PRAMの書き込み時間削減に適した符号
2009 - 2010 遅延故障テスト容易化スキャン設計に対するテストデータ量削減法の考案
2007 - 2009 ソフトエラー対策VLSI回路の考案
2003 - フォールトトレラントプログラマブルチップの設計
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Papers (76)：
Hisato Kashihara, Josaphat Tetuko Sri Sumantyo, Yuta Izumi, Koichi Ito, Steven Gao, Kazuteru Namba. X-Band Microstrip Array Antenna for UAV Onboard Full Circularly Polarized Synthetic Aperture Radar. IEEE Transactions on Antennas and Propagation. 2023. 71. 2. 1943-1948
Keisuke Kozu, Yuya Tanabe, Masato Kitakami, Kazuteru Namba. Low Power Neural Network by Reducing SRAM Operating Voltage. IEEE Access. 2022. 10. 116982-116986
Yuta Yamamoto, Kazuteru Namba. Complete double node upset tolerant latch using C-element. IEICE Trans. Inf. & Syst. 2020. E103-D. 10. 2125-2132
Kazuteru Namba. Master-slave FF using DICE capable of tolerating soft errors occurring around clock edge. IEICE Trans. Inf. & Syst. 2020. E103-D. 4. 892-895
Kazuteru Namba, Fabrizio Lombardi. Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM). IEEE Trans. Comput. 2019. 68. 2. 301-306
ｍore...
MISC (41)：
SBIAI Takieddine, NAMBA Kazuteru, ITO Hideo. A Dynamically Configurable NoC Test Access Mechanism. Technical report of IEICE. VLD. 2011. 111. 324. 49-54
Oishi Koshi, Namba Kazuteru, Ito Hideo, Sumantyo Josaphat Tetuko Sri. CP-SAR Image Processing System Using Two FPGA Board and PC in UAV. IEICE technical report. 2011. 111. 323. 37-41
SBIAI Takieddine, NAMBA Kazuteru, ITO Hideo. A Dynamically Configurable NoC Test Access Mechanism. IEICE technical report. Dependable computing. 2011. 111. 325. 49-54
AKAGAWA Masato, NAMBA Kazuteru, ITO Hideo. Improvement of Test Data Compression Rate for Chiba-Scan Testing by Reconstructing Scan Chain. IEICE technical report. Dependable computing. 2011. 111. 325. 121-126
A Dynamically Configurable NoC Test Access Mechanism. 2011. 2011. 9. 1-6
ｍore...
Patents (11)：
半導体集積回路及び半導体集積回路の検査方法
半導体集積回路及びその遅延測定方法
半導体集積回路
半導体集積回路
エラートレラント方法及びその方法を実現可能な半導体集積回路
ｍore...
Lectures and oral presentations (45)：
Stuck-at Fault Tolerance in DNN Using Outliers and Sampling
(Japan-Korea Joint Workshop on Complex Communication Sciences 2023)
A Study on Design and Challenges of ros2-fuzz
(Japan-Korea Joint Workshop on Complex Communication Sciences 2023)
Stuck-at fault tolerance in DNN using statistical data
(IEEE Pacific Rim International Symposium on Dependable Computing 2022)
A Double Node Upset tolerant SR latch using C-element
(IEEE Int'l Conf. Consum. Electron. Taiwan 2022)
Edge Triggered D Flip-Flop Using Complementarity of DICE
(IEEE Workshop on RTL and High Level Testing 2021)
ｍore...
Education (1)：
1993 - 2002 Tokyo IT
Professional career (1)：
Ph. D (Tokyo IT)
Work history (2)：
2002/11 - 現在 Chiba univ.
2002/04 - 2002/10 Tokyo IT
Committee career (2)：
2019/04 - 現在 電子情報通信学会 ディペンダブルコンピューティング研究会 専門委員
2011/04 - 現在 電子情報通信学会 機能集積情報システム研究会 専門委員
Association Membership(s) (3)：
INFORMATION PROCESSING SOCIETY OF JAPAN
, IEEE
, THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS
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