Rchr
J-GLOBAL ID：200901052474874077
Update date: Jul. 12, 2023
Tsutsui Kazuo
ツツイ カズオ | Tsutsui Kazuo
Affiliation and department：
Job title：
Specially Appointed Professor
Research field (2)：
Electronic devices and equipment
, Applied materials
Research keywords (10)：
integrated devices
, heteroepitaxy
, device process
, electronic materials
, electron devices
, 集積デバイス
, 異種材料ヘテロ
, デバイスプロセス技術
, 電子材料
, 電子デバイス
Research theme for competitive and other funds (6)：
- resonant tunneling devices
- Ultra shallow junctions using plasma doping method
- Heteroepitaxy and its applications
- 共鳴トンネルデバイス
- プラズマドーピング法による極浅接合形成
- ヘテロエピタキシーとデバイス応用
Show all
MISC (244)：
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K. Kakushima, T. Koyanagi, K. Tachi, J. Song, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai. Characterization of flatband voltage roll-off and roll-up behavior in La2O3/silicate gate dielectric. SOLID-STATE ELECTRONICS. 2010. 54. 7. 720-723
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K. Kakushima, K. Tachi, M. Adachi, K. Okamoto, S. Sato, J. Song, T. Kawanago, P. Ahmet, K. Tsutsui, N. Sugii, et al. Interface and electrical properties of La-silicate for direct contact of high-k with silicon. SOLID-STATE ELECTRONICS. 2010. 54. 7. 715-719
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K. Kakushima, T. Koyanagi, K. Tachi, J. Song, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai. Characterization of flatband voltage roll-off and roll-up behavior in La2O3/silicate gate dielectric. SOLID-STATE ELECTRONICS. 2010. 54. 7. 720-723
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K. Kakushima, K. Tachi, M. Adachi, K. Okamoto, S. Sato, J. Song, T. Kawanago, P. Ahmet, K. Tsutsui, N. Sugii, et al. Interface and electrical properties of La-silicate for direct contact of high-k with silicon. SOLID-STATE ELECTRONICS. 2010. 54. 7. 715-719
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M. K. Bera, J. Song, P. Ahmet, K. Kakushima, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai. Yttrium-scandium oxide as high-k gate dielectric for germanium metal-oxide-semiconductor devices. SEMICONDUCTOR SCIENCE AND TECHNOLOGY. 2010. 25. 6. 065008
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Books (2)：
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よくわかる電子デバイス
オーム社 1999
-
表面科学シリーズ4 表面・界面の電子状態
丸善 1987
Lectures and oral presentations (193)：
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Electrical Characteristics of Rare Earth (La, Ce, Pr and Tm) Oxides/Silicates Gate Dielectric
(China Semiconductor Technology International Conference 2010)
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Fabrication of SB-MOSFETs on SOI Substrate Using Ni Silicide Containing Er Interlayer
(China Semiconductor Technology International Conference 2010)
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Performance of Silicon Ballistic Nanowire MOSFET with Diverse Orientations and Diameters
(China Semiconductor Technology International Conference 2010)
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Depth Profiling of Chemical Bonding States of Impurity Atoms and Their Correlation with Electrical Activity in Si Shallow Junctions
(IEEE IWJT 2010 Extended Abstracts 2010 International Workshop on Junction Technology 2010)
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Vacancy-Type Defects in Ultra-Shallow Junctions Fabricated Using Plasma Doping Studied by Positron Annihilation
(IEEE IWJT 2010 Extended Abstracts 2010 International Workshop on Junction Technology 2010)
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Education (3)：
- - 1986 Tokyo Institute of Technology Graduate School, Division of Integrated Science and Engineering
- - 1986 東京工業大学大学院 大学院総合理工学研究科 電子システム
- - 1981 Tokyo Institute of Technology School of Engineering
Professional career (1)：
Work history (4)：
- 1990 - -:
- 1990 - -:東京工業大学 助教授
- 1986 - -:
- 1986 - -:東京工業大学 助手
Association Membership(s) (4)：
IEEE EDS
, 電子情報通信学会
, IEEE EDS
, 応用物理学会
