Rchr
J-GLOBAL ID:200901054357338230   Update date: May. 15, 2020

Yano Seiken

ヤノ セイケン | Yano Seiken
Affiliation and department:
Research field  (1): Communication and network engineering
Research keywords  (4): デイジタル回路 ,  デイジタルシステム設計 ,  Digital Circuit ,  Digital System Design
Research theme for competitive and other funds  (4):
  • 低消費電力設計に関する研究
  • 試験容易化設計・技術に関する研究
  • Study on low power design.
  • Study on design-for-testability.
MISC (9):
Patents (2):
  • 記憶回路(平2-15090)
  • Bit. Slice type Arithmetic Adder Circuit Using Exclusive-OR Logic for use with a Look-Ahead Circuit(usp.4764886)
Education (4):
  • - 1998 Osaka University
  • - 1998 Osaka University Graduate School, Division of Engineering
  • - 1965 Osaka University School of Engineering
  • - 1965 Osaka University Faculty of Engineering
Professional career (1):
  • (BLANK) (Osaka University)
Association Membership(s) (3):
IEEE ,  情報処理学会 ,  電子情報通信学会
※ Researcher’s information displayed in J-GLOBAL is based on the information registered in researchmap. For details, see here.

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