Miyashita Hiroshi

ミヤシタヒロシ | Miyashita Hiroshi

Affiliation and department：
Job title： Professor

Research field (4)： Electronic devices and equipment , Applied mathematics and statistics , Basic mathematics , Information theory

Research keywords (6)：情報数理 , 応用数理 , 大規模集積回路のCAD , Informatics , Applied Mathematics , VLSI CAD

Research theme for competitive and other funds (4)：

数理最適化
VLSIの性能指向レイアウト手法
Mathematical Optimization
Performance-Driven Layout Algorithms for VLSI

MISC (16)：

J Li, H Miyashita. Thermal-aware placement based on FM partition scheme and force-directed heuristic. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES. 2006. E89A. 4. 989-995
J Li, JB Yu, H Miyashita. An incremental placement algorithm for building block layout design based on the O-tree representation. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES. 2005. E88A. 12. 3398-3404
Y Kubo, H Miyashita, Y Kajitani, K Tateishi. Equidistance routing in high-speed VLSI layout design. INTEGRATION-THE VLSI JOURNAL. 2005. 38. 3. 439-449
Y Kubo, H Miyashita, Y Kajitani, K Tateishi. Equidistance routing in high-speed VLSI layout design. INTEGRATION-THE VLSI JOURNAL. 2005. 38. 3. 439-449
Dimension of partial orders and its application to rectangle packing(共著). Research Institute for Mathematical Sciences Kokyuroku. 2003. 1340, pp.65-76

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Patents (5)：

レイアウトの詳細コンパクション方式 (特開平 4-37156)
レイアウトのシンボリック設計方式 (特開平 4-37155)
多重格子制約を持つレイアウトのコンパクション方法 (特開平 8-287117)
レイアウトのコンパクション方式 (特許第1836160号)
レイアウトのコンパクション方式

Books (1)：

数理情報科学事典(共著)
朝倉書店 1995

Lectures and oral presentations (12)：

Efficient thermal via planning for placement of 3D integrated circuits
(2007 IEEE International Symposium on Circuits and Systems 2007)
Thermal-aware placement using Lagrangian relaxation combined with a partition scheme
(2006 International Conf. on Communications, Circuits and Systems 2006)
Post-placement thermal via planning for 3D integrated circuits
(The 2006 IEEE Asia Pacific Conference on Circuits and Systems 2006)
Thermal-aware placement based on FM partition scheme and force-directed heuristic
(The 18th Workshop on Circuits and Systems in Karuizawa 2005)
Stochastic equi-length channel routing with channel height minimization
(The 20th Commemorative International Technical Conference on Cirsuits/Systems, Computers and Communications (ITC-CSCC 2005) 2005)

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Professional career (2)：

Master of Science (Tokyo Institute of Technology)
Doctor of Engineering (Tokyo Institute of Technology)

Association Membership(s) (12)：

アメリカ工業および応用数学会(Society for Industrial and Applied Mathematics) , アメリカ電気電子学会(The Institute of Electrical and Electronics Engineers, Inc) , 日本応用数理学会 , 情報処理学会 , 電子情報通信学会 , The Society for Industrial and Applied Mathematics , Inc. , The Institute of Electrical and Electronics Engineers , Japan Society for Industrial and Applied Mathematics , Information Processing Society of Japan , Information and Communication Engineers , The Institute of Electronics

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