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ArticleJ-GLOBAL ID:200902000037637531整理番号:88A0044336

On-line error-detectable high-speed multiplier using redundant binary representation and three-rail logic.

冗長2進表現と3レール論理を用いたオンライン誤り検出可能高速乗算器

著者:TAKAGI N(Kyoto Univ., Kyoto, JPN)、YAJIMA S(Kyoto Univ., Kyoto, JPN)
資料名:IEEE Trans Comput 巻:36 号:11 ページ:1310-1317
発行年:1987年11月
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About J-GLOBAL

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