Art
J-GLOBAL ID：200902000037637531   Reference number：88A0044336

On-line error-detectable high-speed multiplier using redundant binary representation and three-rail logic.

冗長2進表現と3レール論理を用いたオンライン誤り検出可能高速乗算器
Author (2)：
TAKAGI N

About TAKAGI N

(Kyoto Univ., Kyoto, JPN)

About Kyoto Univ., Kyoto, JPN

, 
YAJIMA S

About YAJIMA S

(Kyoto Univ., Kyoto, JPN)

About Kyoto Univ., Kyoto, JPN


Material：
IEEE Transactions on Computers  (IEEE Trans Comput)

About IEEE Transactions on Computers


Volume： 36  Issue： 11  Page： 1310-1317  Publication year： Nov. 1987 
JST Material Number： C0233A  ISSN： 0018-9340  CODEN： ICTOB4  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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VLSI

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,...
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Thesaurus term/Semi thesaurus term
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All keywords is available on JDreamIII(charged).
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チップ【IC】

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JST classification (1)：
JST classification
Category name(code) classified by JST.
Other digital computer systems 
(JC02050G)

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Terms in the title (7)：
Terms in the title
Keywords automatically extracted from the title.
冗長

About 冗長

, 
表現

About 表現

, 
レール

About レール

, 
論理

About 論理

, 
オンライン

About オンライン

, 
誤り検出

About 誤り検出

, 
乗算器

About 乗算器


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