Art
J-GLOBAL ID：200902001840166889   Reference number：84A0438466

Optimization of device area and overall delay for CMOS VLSI designs.

CMOS VLSI設計に対する装置面積と全遅延の最適化
Author (1)：
LEWIS E T

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(Raytheon Co., MA)

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Material：
Proceedings of the IEEE  (Proc IEEE)

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Volume： 72  Issue： 6  Page： 670-689  Publication year： Jun. 1984 
JST Material Number： D0378A  ISSN： 0018-9219  CODEN： IEEPAD  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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MOS integrated circuit

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,...
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Thesaurus term/Semi thesaurus term
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All keywords is available on JDreamIII(charged).
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topology

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,...
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JST classification (1)：
JST classification
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Semiconductor integrated circuit 
(NC03162T)

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Terms in the title (5)：
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CMOS

About CMOS

, 
VLSI設計

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, 
面積

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, 
遅延

About 遅延

, 
最適化

About 最適化


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