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ArticleJ-GLOBAL ID:200902001840166889整理番号:84A0438466

Optimization of device area and overall delay for CMOS VLSI designs.

CMOS VLSI設計に対する装置面積と全遅延の最適化

著者:LEWIS E T(Raytheon Co., MA)
資料名:Proc IEEE 巻:72 号:6 ページ:670-689
発行年:1984年06月
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J-GLOBAL: Linking, Expanding and Sparking

About J-GLOBAL

Linking

J-GLOBAL links information that represents the key to research and development. For example, linking articles and patents with people (authors and inventors) enables the extraction of a sequence of information.
It’s useful for making new discoveries and uncovering new information.

Expanding

The system enables searches of similar kinds of content through linkage with external sites.
It helps you to obtain knowledge from dissimilar fields and discover concepts that cross the boundaries of specialisms.

Sparking

Through repeated linkage and expansioniteration, J-GLOBAL provides unexpected hints for problem-solving and the illumination of new ideas.