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ArticleJ-GLOBAL ID:200902002070040764整理番号:85A0426947

Reactance compensation matches FET circuits.

FET回路を整合するリアクタンス補償

著者:CAMARGO E(Univ. Sao Paulo, Brazil)、CONSONI D(Univ. Sao Paulo, Brazil)、SOARES R A(Centre National d’Etudes de Telecommunications, France)
資料名:Microw RF 巻:24 号:6 ページ:93-95
発行年:1985年06月
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About J-GLOBAL

Linking

J-GLOBAL links information that represents the key to research and development. For example, linking articles and patents with people (authors and inventors) enables the extraction of a sequence of information.
It’s useful for making new discoveries and uncovering new information.

Expanding

The system enables searches of similar kinds of content through linkage with external sites.
It helps you to obtain knowledge from dissimilar fields and discover concepts that cross the boundaries of specialisms.

Sparking

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