Art
J-GLOBAL ID：200902002087038429   Reference number：92A0584997

A write-invalidate cache coherence protocol for MIN-based multiprocessors.

MINベース・マルチプロセッサ用書込み無効型キャッシュコヒーレンス・プロトコル
Author (3)：
THAZHUTHAVEETIL M J

About THAZHUTHAVEETIL M J

(Pennsylvania State Univ., PA, USA)

About Pennsylvania State Univ., PA, USA

, 
ALGUDADY M S

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, 
DAS C R

About DAS C R


Material：
International Journal of Mini and Microcomputers  (Int J Mini Microcomput)

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Volume： 14  Issue： 1  Page： 39-44  Publication year： 1992 
JST Material Number： T0481A  ISSN： 0702-0481  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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multiprocessor system

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,...
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Thesaurus term/Semi thesaurus term
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キャッシュコヒーレンス

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JST classification (1)：
JST classification
Category name(code) classified by JST.
Memory systems 
(JC02040V)

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Terms in the title (5)：
Terms in the title
Keywords automatically extracted from the title.
マルチプロセッサ

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, 
書込み

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, 
無効

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, 
キャッシュコヒーレンス

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, 
プロトコル

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