Art
J-GLOBAL ID：200902015541108326   Reference number：88A0152144

Parallel techniques for chip placement by simulated annealing on shared memory systems.

共用メモリシステム上の疑似アニーリングによるチップ配置の並列技術
Author (3)：
DAREMA F

About DAREMA F

(IBM T.J. Watson Research Center, NY, USA)

About IBM T.J. Watson Research Center, NY, USA

, 
KIRKPATRICK S

About KIRKPATRICK S

(IBM T.J. Watson Research Center, NY, USA)

About IBM T.J. Watson Research Center, NY, USA

, 
NORTON V A

About NORTON V A

(IBM T.J. Watson Research Center, NY, USA)

About IBM T.J. Watson Research Center, NY, USA


Material：
Proceedings. IEEE International Conference on Computer Design: VLSI in Computers & Processors  (Proceedings. International Conference on Computer Design)

About Proceedings. IEEE International Conference on Computer Design: VLSI in Computers & Processors


Volume： 1987  Page： 87-90  Publication year： 1987 
JST Material Number： D0858B  ISSN： 1063-6404  Document type： Proceedings
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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multicomputer system

About multicomputer system

,...
Semi thesaurus term：
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
チップ【IC】

About チップ【IC】


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JST classification (1)：
JST classification
Category name(code) classified by JST.
Digital computer systems in general 
(JC02010O)

About Digital computer systems in general

Terms in the title (3)：
Terms in the title
Keywords automatically extracted from the title.
共用

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, 
メモリシステム

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, 
アニーリング

About アニーリング


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