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ArticleJ-GLOBAL ID:200902015541108326整理番号:88A0152144

Parallel techniques for chip placement by simulated annealing on shared memory systems.

共用メモリシステム上の疑似アニーリングによるチップ配置の並列技術

著者:DAREMA F(IBM T.J. Watson Research Center, NY, USA)、KIRKPATRICK S(IBM T.J. Watson Research Center, NY, USA)、NORTON V A(IBM T.J. Watson Research Center, NY, USA)
資料名:Proc IEEE Int Conf Comput Des VLSI Comput Process 巻:1987 ページ:87-90
発行年:1987年
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