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J-GLOBAL ID：200902015557089070   Reference number：89A0422557

Analysis and design of a voltage multiplier circuit.

倍電圧整流回路の解析と設計
Author (1)：
SEDAKA KAZUO

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(育英工高専)

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Material：
育英工業高等専門学校研究紀要  (Bulletin of Salesian Polytechnic)

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Issue： 15  Page： 27-31  Publication year： Mar. 1989 
JST Material Number： S0862A  ISSN： 0386-345X  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： JAPANESE (JA)
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full wave rectification

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,...
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JST classification (1)：
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Rectifiers 
(NB08040M)

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Terms in the title (3)：
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整流回路

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, 
解析

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, 
設計

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