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ArticleJ-GLOBAL ID:200902015601588365整理番号:87A0455004

Designing VLSI network nodes to reduce memory traffic in a shared memory parallel computer.

メモリ共用並列コンピュータにおけるメモリトラヒックを削減するVLSIネットワークノードの設計

著者:DICKEY S(New York Univ., NY, USA)、GOTTLIEB A(New York Univ., NY, USA)、KENNER R(New York Univ., NY, USA)・・・
資料名:Circuits Syst Signal Process 巻:6 号:2 ページ:217-238
発行年:1987年
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