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ArticleJ-GLOBAL ID:200902015673856534整理番号:81A0121334

LSI design considerations for multistage interconnection networks for parallel processing systems.

並列処理システムの多段結合回路網のLSI設計

著者:SMITH S D(Univ. Wisconsin)
資料名:Proc Hawaii Int Conf Syst Sci 巻:14th 号:1 ページ:219-227
発行年:1981年
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