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ArticleJ-GLOBAL ID:200902015713830010整理番号:81A0145746

Digital logic and circuit design for improved power-delay product in LSI.

LSIの改善された電力遅延積のためのディジタル論理および回路設計

著者:SCAVUZZO R J(Bell Telephone Lab. Inc., Pennsylvania)
資料名:Proc IEEE Int Conf Circuits Comput 1980 ページ:693-696
発行年:1980年
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