Art
J-GLOBAL ID：200902015713830010   Reference number：81A0145746

Digital logic and circuit design for improved power-delay product in LSI.

LSIの改善された電力遅延積のためのディジタル論理および回路設計
Author (1)：
SCAVUZZO R J

About SCAVUZZO R J

(Bell Telephone Lab. Inc., Pennsylvania)

About Bell Telephone Lab. Inc., Pennsylvania


Material：
Proceedings. IEEE International Conference on Circuits and Computers, 1980  (ICCC 80)

About Proceedings. IEEE International Conference on Circuits and Computers, 1980


Page： 693-696  Publication year： 1980 
JST Material Number： K19810059  Document type： Proceedings
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
Thesaurus term：
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
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LSI

About LSI

,...
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JST classification (1)：
JST classification
Category name(code) classified by JST.
Logic circuits 
(NC05070B)

About Logic circuits

Terms in the title (5)：
Terms in the title
Keywords automatically extracted from the title.
LSI

About LSI

, 
電力遅延積

About 電力遅延積

, 
ディジタル

About ディジタル

, 
論理

About 論理

, 
回路設計

About 回路設計


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