Art
J-GLOBAL ID：200902015717337467   Reference number：85A0455037

Fault-tolerant systems using ternary decision circuits.

三値決定回路による障害許容システム
Author (2)：
HU M

About HU M

(Shanghai Inst. Railway Technology, CHN)

About Shanghai Inst. Railway Technology, CHN

, 
MOUFTAH H T

About MOUFTAH H T

(Queen’s Univ., Canada)

About Queen’s Univ., Canada


Material：
Proceedings. IEEE International Symposium on Multiple-Valued Logic  (Proceedings. International Symposium on Multiple-Valued Logic)

About Proceedings. IEEE International Symposium on Multiple-Valued Logic


Volume： 15th  Page： 331-336  Publication year： 1985 
JST Material Number： B0822B  ISSN： 0195-623X  Document type： Proceedings
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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three-valued logic

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JST classification (1)：
JST classification
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Logic circuits 
(NC05070B)

About Logic circuits

Terms in the title (4)：
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三値

About 三値

, 
決定回路

About 決定回路

, 
障害

About 障害

, 
許容

About 許容


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