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ArticleJ-GLOBAL ID:200902019041270858整理番号:82A0463990

A critique of network speed in VLSI models of computation.

計算のVLSIモデルにおける回路網の速度の評価法

著者:BILARDI G(Univ. Illinois at Urbana‐Champaign)、PRACCHI M(Univ. Illinois at Urbana‐Champaign)、PREPARATA F P(Univ. Illinois at Urbana‐Champaign)
資料名:IEEE J Solid-State Circuits 巻:17 号:4 ページ:696-702
発行年:1982年08月
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