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ArticleJ-GLOBAL ID:200902131050230740整理番号:99A0581236

過渡的デバイスシミュレーションによるサブ0.1μmCMOSの内部容量解析

Evaluation of Sub-0.1.MU.m CMOS Internal Capacitance by using Transient Device Simulation.

著者:辻清孝(NEC)、竹内潔(NEC)
資料名:応用物理学会学術講演会講演予稿集 巻:59th 号:2 ページ:791
発行年:1998年09月
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