Art
J-GLOBAL ID:200902165014676610   Reference number:02A0026419

Universal-Vdd 0.65-2.0-V 32-kB Cache Using a Voltage-Adapted Timing-Generation Scheme and a Lithographically Symmetrical Cell.

電圧適応タイミング発生スキームとリソグラフィー的対称セルを使った汎用Vdd 0.65~2.0V,32kBキャッシュ
Author (9):
Material:
Volume: 36  Issue: 11  Page: 1738-1744  Publication year: Nov. 2001 
JST Material Number: B0761A  ISSN: 0018-9200  CODEN: IJSCBC  Document type: Article
Article type: 原著論文  Country of issue: United States (USA)  Language: ENGLISH (EN)
Thesaurus term:
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
,...
Semi thesaurus term:
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
,...
   To see more with JDream III (charged).   {{ this.onShowAbsJLink("http://jdream3.com/lp/jglobal/index.html?docNo=02A0026419&from=J-GLOBAL&jstjournalNo=B0761A") }}
JST classification (3):
JST classification
Category name(code) classified by JST.
General-purpose arithmetic and control units  ,  Semiconductor integrated circuit  ,  Digital computer systems in general 

Return to Previous Page