A 29ns 64Mb DRAM with Hierarchical Array Architecture.

NAKAMURA M; TAKAHASHI T; AKIBA T; KITSUKAWA G; MORINO M; SEKIGUCHI T; ASANO I; KOMATSUZAKI K; SATOH K

Art

J-GLOBAL ID：200902165064805097 Reference number：95A0834167

A 29ns 64Mb DRAM with Hierarchical Array Architecture.

階層型アレイアーキテクチャの29ns,64Mb,DRAM

Publisher site Copy service {{ this.onShowCLink("http://jdream3.com/copy/?sid=JGLOBAL&noSystem=1&documentNoArray=95A0834167&COPY=1") }}
Access JDreamⅢ for advanced search and analysis. {{ this.onShowJLink("http://jdream3.com/lp/jglobal/index.html?docNo=95A0834167&from=J-GLOBAL&jstjournalNo=D0753A") }}

Author (9)： , , , , , , , ,
Material：
Volume： 38 Page： 246-247,373 Publication year： Feb. 1995
JST Material Number： D0753A ISSN： 0193-6530 Document type： Proceedings
Article type：原著論文 Country of issue： United States (USA) Language： ENGLISH (EN)

,...

To see more with JDream III (charged). {{ this.onShowAbsJLink("http://jdream3.com/lp/jglobal/index.html?docNo=95A0834167&from=J-GLOBAL&jstjournalNo=D0753A") }}

Semiconductor integrated circuit , Memory units

, , ,

Return to Previous Page