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ArticleJ-GLOBAL ID:200902165064805097整理番号:95A0834167

A 29ns 64Mb DRAM with Hierarchical Array Architecture.

階層型アレイアーキテクチャの29ns,64Mb,DRAM

著者:NAKAMURA M(Hitachi Ltd., Tokyo, JPN)、TAKAHASHI T(Hitachi Ltd., Tokyo, JPN)、AKIBA T(Hitachi Device Engineering Corp., Chiba, JPN)・・・
資料名:Dig Tech Pap IEEE Int Solid State Circuits Conf 巻:38 ページ:246-247,373
発行年:1995年02月
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J-GLOBAL: Linking, Expanding and Sparking

About J-GLOBAL

Linking

J-GLOBAL links information that represents the key to research and development. For example, linking articles and patents with people (authors and inventors) enables the extraction of a sequence of information.
It’s useful for making new discoveries and uncovering new information.

Expanding

The system enables searches of similar kinds of content through linkage with external sites.
It helps you to obtain knowledge from dissimilar fields and discover concepts that cross the boundaries of specialisms.

Sparking

Through repeated linkage and expansioniteration, J-GLOBAL provides unexpected hints for problem-solving and the illumination of new ideas.