Art

J-GLOBAL ID：200902165125869077   Reference number：01A0333558

Backpropagation Algorithm for LOGic Oriented Neural Networks with Quantized Weights and Multilevel Threshold Neurons.

量子化重みと多段階しきい値ニューロンを用いた論理指向ニューラルネットワークのためのバックプロパゲーションアルゴリズム

Author (3)： KAMIO T (Hiroshima City Univ., Hiroshima-shi, JPN) ,  FUJISAKA H (Hiroshima City Univ., Hiroshima-shi, JPN) ,  MORISUE M (Hiroshima City Univ., Hiroshima-shi, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E84-A  Issue： 3  Page： 705-712  Publication year： Mar. 01, 2001 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *back propagation ,...

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JST classification (1)： Artificial intelligence  (JE08000Z)

Reference (9)：

• MORIE, T. An all-analog expandable neural network LSI with on-chip backpropagation learning. IEEE J. Solid-State Circuits. 1994, 29, 9, 1086-1093
• MORIE, T. Analog LSI implementation of self-learning neural networks. Computers and Electrical Engineering. 1999, 25, 5, 339-355
• NAGATA, M. A PWM signal processing core circuit based on a switched current integration technique. IEEE J. Solid-State Circuits. 1998, 33, 1, 53-60
• UCHIMURA, K. A high-speed digital neural network chip with low-power chain-reaction architecture. IEEE J. Solid-State Circuits. 1992, 27, 12, 1862-1867
• KONDO, Y. A 1.2 GFLOPS neural network chip exhibiting fast convergence. Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC). 1994, 218-219

Terms in the title (6)： 量子化 ,  多段 ,  しきい値 ,  ニューロン ,  論理 ,  ニューラルネットワーク