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ArticleJ-GLOBAL ID:200902165133700650整理番号:93A0792095

論理合成向き仮想遅延値の精度向上

Logical Delay Model for Logic Synthesis.

著者:野地保(三菱電機)、浜田英幸(三菱電機)、浦野真帆(三菱電機)
資料名:情報処理学会シンポジウム論文集 巻:93 号:5 ページ:65-68
発行年:1993年08月
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