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ArticleJ-GLOBAL ID:200902165137678196整理番号:98A0807358

VLSI Design and Implementation of An Improved Squaring Circuit by Combinational Logic.

組合せ論理による改良されたスクエアリング回路のVLSI設計と実現

著者:ABDEL‐ATY‐ZOHDY H S(Oakland Univ., MI, USA)、HIASAT A A(Oakland Univ., MI, USA)
資料名:Conf Rec Asilomar Conf Signals, Syst Comput 巻:31st 号:Vol.1 ページ:426-429
発行年:1997年
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