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ArticleJ-GLOBAL ID:200902212458465990整理番号:09A0314431

Verilogに基づくRISC MCUの割込みシステムの仕様と検証

The design and verification of RISC MCU?s interrupt system based on Verilog

著者:LING ChaoDong(Yunshun IC Design Res. & Dev. laboratory, Huaqiao Univ., Quanzhou)、KE ZhiBin(Yunshun IC Design Res. & Dev. laboratory, Huaqiao Univ., Quanzhou)、WANG JiaXian(Yunshun IC Design Res. & Dev. laboratory, Huaqiao Univ., Quanzhou)
資料名:Dianzi Jishu Yingyong 巻:34 号:3 ページ:48-51
発行年:2008年
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