Art

J-GLOBAL ID：201602274322601217   Reference number：16A1125640

TSV Array-Based 3D ICs Design Exploration and Optimization

TSVに基づく三次元統合回路の最適化設計に関する研究【JST・京大機械翻訳】

Author (4)： Wang Tianxi (School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University) ,  Jiang Jianfei (School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University) ,  Wang Qin (School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University) ,  Mao Zhigang (School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University)
Material： Weidianzixue yu Jisuanji  (Microelectronics & Computer)
Volume： 33  Issue： 7  Page： 129-132  Publication year： 2016 
JST Material Number： C2387A  ISSN： 1000-7180  Document type： Article
Article type： 原著論文  Country of issue： China (CHN)  Language： CHINESE (ZH)

Abstract/Point： This paper analysis TSV array’...

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Thesaurus term： wiring ,  electric power consumption ,  *optimum design ,  motion estimation ,  reliability(property) ,  redundancy(property) ,  *three dimension
Semi thesaurus term： 三次元集積回路 , 【Automatic Indexing@JST】

Author keywords (3)： 3DIC ,  Back-end design ,  TSV Array

JST classification (2)： Printed circuits  (NA05040O) ,  Semiconductor integrated circuit  (NC03162T)

Terms in the title (4)： TSV ,  統合 ,  最適化設計 ,  研究