Art

J-GLOBAL ID：201702211278436387   Reference number：17A0545166

Linearity Improvement Method of Fast-Chirp Signal for PLL by Using Frequency Detector and Division Ratio Modification

PLLの周波数検出と分周数制御を用いたチャープ信号の線形性向上処理手法

Author (4)： WADA OSAMU (三菱電機) ,  MIZUTANI HIROYUKI (三菱電機) ,  NAKAMIZO HIDEYUKI (三菱電機) ,  TAJIMA KEN'ICHI (三菱電機)
Material： 電子情報通信学会技術研究報告  (IEICE Technical Report (Institute of Electronics, Information and Communication Engineers))
Volume： 116  Issue： 487(ICD2016 118-144)  Page： 51-54  Publication year： Feb. 23, 2017 
JST Material Number： S0532B  ISSN： 0913-5685  Document type： Proceedings
Article type： 原著論文  Country of issue： Japan (JPN)  Language： JAPANESE (JA)

Thesaurus term： *chirp ,  *phase locked loop ,  detection ,  frequency(Hz) ,  *frequency divider ,  feedback ,  separation ,  time ,  error(measure) ,  *linearity
Semi thesaurus term： *Chirp signal ,  周波数検出 ,  周波数誤差 ,  frequency division ,  delay time

JST classification (1)： Frequency conversion circuits  (NC05030J)

Reference (7)：

• Hiroshi Matsumura, Yohei Yagishita, Ikuo Soga, Yoichi Kawano, Taisuke Iwai, “Milimeter-wave linear fast-chirp pulse generator in 65-nm CMOS technology,” Proceedings of the 11th European Microwave, vol. 54, no. 5, pp. 1006-1017, Oct. 2016.
• M. Pichler, A. Stelzer, P. Gulden, C. Seisenberger, and M. Vossiek, “Phase-error measurement and compensation in PLL frequency synthesizers for FMCW sensors-I: Context and Application,” IEEE Trans. Circuit Syst. I, vol. 54, no. 5, pp. 1006-1017, May 2007.
• M. Pichler, A. Stelzer, P. Gulden, C. Seisenberger, and M. Vossiek, “Phase-error measurement and compensation in PLL frequency synthesizers for FMCW sensors-II: Theory,” IEEE Trans. Circuit Syst. I, vol. 54, no. 6, pp. 1224-1235, Jun. 2007.
• Hwanseok Yeo, Sigang Ryu, Yoontaek Lee, Seuk Son, and Jaeha Kim, “A 940MHz-bandwidth 28.8μs period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications,” Proc. ISSCC, pp. 238-240, Jan. 2016.
• W. Wu, R. B. Staszewski, and J. R. Long, “A 56.4 -to- 63.4 GHz multirate all-digital fractional-N PLL for FMCW radar applications in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 5, pp. 1081-1096, May 2014.

Terms in the title (4)： PLL ,  チャープ信号 ,  線形性 ,  手法