Art
J-GLOBAL ID:201702223703950574   Reference number:17A0257857

Implementations of the pixel cache validation platform based on SystemVerilog language

システム言語に基づく画素キャッシュ検証プラットフォームの実現【JST・京大機械翻訳】
Author (4):
Material:
Volume: 42  Issue: 10  Page: 51-53,61  Publication year: 2016 
JST Material Number: C2505A  ISSN: 0258-7998  Document type: Article
Article type: 原著論文  Country of issue: China (CHN)  Language: CHINESE (ZH)
Abstract/Point:
Abstract/Point
Japanese summary of the article(about several hundred characters).
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Based on SystemVerilog,build a...
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Author keywords (4):
JST classification (3):
JST classification
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Operating systems  ,  CAD,CAM  ,  Computer system development 
Terms in the title (5):
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