Art

J-GLOBAL ID：201702239715934722   Reference number：17A0243044

A Framework for Tree-based Checkpointing Architecture on FPGAs

FPGA上のツリーをベースとしたチェックポインティングアーキテクチャのためのフレームワーク

Author (4)： VU Hoang Gia (Nara Inst. of Sci. and Technol.) ,  TAKAMAEDA-YAMAZAKI Shinya (Hokkaido Univ.) ,  NAKADA Takashi (Nara Inst. of Sci. and Technol.) ,  NAKASHIMA Yasuhiko (Nara Inst. of Sci. and Technol.)
Material： 電子情報通信学会技術研究報告  (IEICE Technical Report (Institute of Electronics, Information and Communication Engineers))
Volume： 116  Issue： 415(VLD2016 70-101)  Page： 79-84  Publication year： Jan. 16, 2017 
JST Material Number： S0532B  ISSN： 0913-5685  Document type： Proceedings
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *FPGA ,  *tree structure ,  *checking out ,  *system architecture ,  *constitution ,  hardware description language
Semi thesaurus term： *checkpointing ,  Verilog

JST classification (1)： Semiconductor integrated circuit  (NC03162T)

Reference (11)：

• Bianca Schroeder and Garth A. Gibson, “A Large-Scale Study of Failures in High-Performance Computing Systems,” IEEE transactions on Dependable and Secure Computing, VOL. 7, NO. 4, Oct-Dec 2010.
• F. Cappello, Al Geist, W. Gropp, S. Kale, B. Kramer, M. Snir, “Toward Exascale Resillience 2014 Update,” Journal of Supercomputing Frontiers and Innovations, Vol. 1, No. 1, 2014.
• Dirk Koch, Christian Haubelt and J?rgen Teich, “Efficient Hardware Checkpointing - Concepts, Overhead Analysis, and Implementation,” FPGA'07, pp.188-196, February 18-20, 2007, Monterey, California, USA.
• H. Kalte and M. Porrmann, “Context Saving and Restoring for Multitasking in Reconfigurable Systems,” International Conference on Field Programmable Logic and Applications, pp. 223-228, 2005.
• I H. Simmler, L. Levinson, and R. Manner, “Multitasking on FPGA Coprocessors,” In Proceedings of the 10rd International Conference on Field Programmable Logic and Application (FPL'00), pages 121-130, 2000.

Terms in the title (2)： FPGA ,  フレームワーク