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J-GLOBAL ID:201702231261710705   Reference number:17A0055041

Memory access algorithm for low energy CPU/GPU heterogeneous systems with hybrid DRAM/NVM memory architecture

ハイブリッドDRAM/NVMメモリアーキテクチャを用いた低エネルギーCPU/GPUヘテロシステムのためのメモリアクセスアルゴリズム【Powered by NICT】
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Volume: 2016  Issue: APCCAS  Page: 461-464  Publication year: 2016 
JST Material Number: W2441A  Document type: Proceedings
Article type: 原著論文  Country of issue: United States (USA)  Language: ENGLISH (EN)
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Semiconductor integrated circuit  ,  Memory systems 
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