Art

J-GLOBAL ID：201702239720800839   Reference number：17A0545340

Hardware Accelerator for Online Neural Network Training at Gateway

ゲートウェイにおけるオンラインニューラルネットワーク学習器ハードウェアの提案

Author (2)： SAWAGUCHI SOTA (慶応大 理工) ,  NISHI HIROAKI (慶応大 理工)
Material： 電子情報通信学会技術研究報告  (IEICE Technical Report (Institute of Electronics, Information and Communication Engineers))
Volume： 116  Issue： 511(DC2016 84-108)  Page： 171-176  Publication year： Mar. 02, 2017 
JST Material Number： S0532B  ISSN： 0913-5685  Document type： Proceedings
Article type： 原著論文  Country of issue： Japan (JPN)  Language： JAPANESE (JA)

Thesaurus term： *neural network(biomodel) ,  VLSI ,  FPGA ,  *gateway ,  reconstitution ,  steepest descent method ,  consumed electric power
Semi thesaurus term： SOC ,  dynamic reconfiguration ,  low electric power

JST classification (1)： Artificial intelligence  (JE08000Z)

Reference (9)：

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Terms in the title (6)： ゲートウェイ ,  オンライン ,  ニューラルネットワーク ,  学習 ,  ハードウェア ,  提案