菅野卓雄

スガノタクオ | Sugano Takuo

所属機関・部署：

研究分野 (1件)：電子デバイス、電子機器

研究キーワード (1件)：半導体電子工学

競争的資金等の研究課題 (2件)：

論文 (11件)：

Tatsuya Yamada, Yoshikata Nakajima, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano. Improvement of electrical characteristics of local BOX MOSFETs by heavily doped structures and elucidation of the related mechanism. JOURNAL OF COMPUTATIONAL ELECTRONICS. 2014. 13. 2. 400-407
Tatsuya Yamada, Yoshikata Nakajima, Tatsuro Hanajiri, Takuo Sugano. Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications (vol 60, pg 260, 2013). IEEE TRANSACTIONS ON ELECTRON DEVICES. 2013. 60. 12. 4281-4283
Tatsuya Yamada, Shumpei Abe, Yoshikata Nakajima, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano. Quantitative Extraction of Electric Flux in the Buried-Oxide Layer and Investigation of Its Effects on MOSFET Characteristics. IEEE TRANSACTIONS ON ELECTRON DEVICES. 2013. 60. 12. 3996-4001
Tatsuya Yamada, Yoshikata Nakajima, Tatsuro Hanajiri, Takuo Sugano. Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications. IEEE TRANSACTIONS ON ELECTRON DEVICES. 2013. 60. 1. 260-267
Yoshikata Nakajima, Yukitoshi Watanabe, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano. Local-Stress-Induced Trap States in SOI Layers With Different Levels of Roughness at SOI/BOX Interfaces. IEEE ELECTRON DEVICE LETTERS. 2011. 32. 3. 237-239

MISC (2件)：

Yoshikata Nakajima, Yukitoshi Watanabe, Tatsuro Hanajiri, Toru Toyabe, Takuo Sugano. Correlation between high-density trap states and local stress near SOI/BOX interface in SIMOX wafers. 2009 International Semiconductor Device Research Symposium, ISDRS '09. 2009
菅野卓雄. 工学における量子力学 (量子力学と先端技術<特集>). 数理科学. 1987. 25. 4. p5-11

学歴 (1件)：

学位 (1件)：

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菅野 卓雄