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J-GLOBAL ID：201702272800472603   整理番号：17A0754799

48積層WL層を持つ256Gb3b/Cell V NANDフラッシュメモリ【Powered by NICT】

256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers

著者 (29件)： Kang Dongku (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Jeong Woopyo (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Kim Chulbum (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Kim Doo-Hyun (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Cho Yong Sung (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Kang Kyung-Tae (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Ryu Jinho (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Kang Kyung-Min (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Lee SungYeon (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Kim Wandong (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Lee Hanjun (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Yu Jaedoeg (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Choi Nayoung (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Jang Dong-Su (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Lee Cheon An (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Min Young-Sun (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Kim Moo-Sung (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Park An-Soo (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Son Jae-Ick (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Kim In-Mo (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Kwak Pansuk (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Jung Bong-Kil (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Lee Doo-Sub (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Kim Hyunggon (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Ihm Jeong-Don (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Byeon Dae-Seok (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Lee Jin-Yup (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Park Ki-Tae (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea) ,  Kyung Kye-Hyun (Flash Product and Technology, Memory Business, Samsung Electronics Company Ltd., Hwaseong, South Korea)
資料名： IEEE Journal of Solid-State Circuits  (IEEE Journal of Solid-State Circuits)
巻： 52  号： 1  ページ： 210-217  発行年： 2017年 
JST資料番号： B0761A  ISSN： 0018-9200  CODEN： IJSCBC  資料種別： 逐次刊行物 (A)
記事区分： 原著論文  発行国： アメリカ合衆国 (USA)  言語： 英語 (EN)

抄録/ポイント： 3b MLC技術を用いた48WL積層256Gb V NANDフラッシュメモリを提案した。劣化したWL負荷と変動のようないくつかの垂直スケールダウン効果を検討した。性能を高めるために,逆読出し方式と可変パルス方式は,不均一WL特性に対処した。性能を改善するため,二重状態機械アーキテクチャはBLおよびWLの最適タイミングを達成するために提案した。,PVT変化に対してロバストIOドライバ強度を維持するために,温度補償を有する埋め込みZQキャリブレーション技術を紹介した。第三世代V NAND技術で製作したチップはプログラムスループットの2.6~53.2で741MB/sとGb/mm~2の密度を達成した。Copyright 2017 The Institute of Electrical and Electronics Engineers, Inc. All Rights reserved. Translated from English into Japanese by JST【Powered by NICT】

シソーラス用語： 温度補償 ,  *フラッシュメモリ ,  パルス ,  計算機アーキテクチャ ,  ロバスト性
準シソーラス用語： スケールダウン ,  *NAND , 【Automatic Indexing@JST】

分類 (2件)： 半導体集積回路  (NC03162T) ,  増幅回路  (NC05040U)

タイトルに関連する用語 (1件)： NANDフラッシュメモリ