文献
J-GLOBAL ID:201302246318797530
整理番号:13A1087320
高帯域幅積層DRAMによる電力効率のよいLSIデバイス用の微細ピッチCu再配置配線とSnCuマイクロバンピングのプロセス集積
Process integration of fine pitch Cu redistribution wiring and SnCu micro-bumping for power efficient LSI devices with high-bandwidth stacked DRAM
著者 (10件):
EZAWA Hirokazu
(Toshiba Corp., Semiconductor & Storage Products Co., JPN)
,
EZAWA Hirokazu
(The Graduate School of Information, Production and Systems, Waseda Univ., JPN)
,
TOGASAKI Takashi
(Toshiba Corp., Corporate Manufacturing Engineering Centre, JPN)
,
MIGITA Tatsuo
(Toshiba Corp., Semiconductor & Storage Products Co., JPN)
,
YAMASHITA Soichi
(Toshiba Corp., Semiconductor & Storage Products Co., JPN)
,
INOHARA Masahiro
(Toshiba Corp., Semiconductor & Storage Products Co., JPN)
,
KOSHIO Yasuhiro
(Toshiba Corp., Semiconductor & Storage Products Co., JPN)
,
FUKUDA Masatoshi
(Toshiba Corp., Semiconductor & Storage Products Co., JPN)
,
MIYATA Masahiro
(Toshiba Corp., Semiconductor & Storage Products Co., JPN)
,
TATSUMI Kohei
(The Graduate School of Information, Production and Systems, Waseda Univ., JPN)
資料名:
Microelectronic Engineering
(Microelectronic Engineering)
巻:
103
ページ:
22-32
発行年:
2013年03月
JST資料番号:
C0406B
ISSN:
0167-9317
CODEN:
MIENEF
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
オランダ (NLD)
言語:
英語 (EN)