文献
J-GLOBAL ID:201302288159956642
整理番号:13A1574635
二重ゲートCNTFETに基づく再構成可能論理の回路設計
Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs
著者 (3件):
KOBAYASHI Manabu
(Dep. of Information Sci., School of Engineering, Shonan Inst. of Technol.)
,
NINOMIYA Hiroshi
(Dep. of Information Sci., School of Engineering, Shonan Inst. of Technol.)
,
WATANABE Shigeyoshi
(Dep. of Information Sci., School of Engineering, Shonan Inst. of Technol.)
資料名:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)
(IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers))
巻:
E96-A
号:
7
ページ:
1642-1644 (J-STAGE)
発行年:
2013年
JST資料番号:
F0699C
ISSN:
0916-8508
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
日本 (JPN)
言語:
英語 (EN)