文献
J-GLOBAL ID:201302298351289892
整理番号:13A1106397
直接数値周波数シンセサイザに対して設計した5.3-GHz32ビット累算器
A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer
著者 (6件):
Chen Jianwu
(Inst. of Microelectronics,Chinese Acad. of Sciences Key Lab. of Microelectronics Devices & Integrated ...)
,
Wu Danyu
(Inst. of Microelectronics,Chinese Acad. of Sciences Key Lab. of Microelectronics Devices & Integrated ...)
,
Zhou Lei
(Inst. of Microelectronics,Chinese Acad. of Sciences Key Lab. of Microelectronics Devices & Integrated ...)
,
Wu Jin
(Inst. of Microelectronics,Chinese Acad. of Sciences Key Lab. of Microelectronics Devices & Integrated ...)
,
Jin Zhi
(Inst. of Microelectronics,Chinese Acad. of Sciences Key Lab. of Microelectronics Devices & Integrated ...)
,
Liu Xinyu
(Inst. of Microelectronics,Chinese Acad. of Sciences Key Lab. of Microelectronics Devices & Integrated ...)
資料名:
Chinese Science Bulletin
(Chinese Science Bulletin)
巻:
57
号:
19
ページ:
2480-2487
発行年:
2012年
JST資料番号:
A0206B
ISSN:
1001-6538
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
中国 (CHN)
言語:
英語 (EN)