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J-GLOBAL ID:201702210046295531
整理番号:17A0328643
種々の予備部品を有するメモリのためのハードウェア効率のよいビルトイン冗長度解析【Powered by NICT】
Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares
著者 (4件):
Kim Jooyoung
(Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea)
,
Lee Woosung
(Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea)
,
Cho Keewon
(Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea)
,
Kang Sungho
(Computer Systems Reliable SOC Laboratory, Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea)
資料名:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
(IEEE Transactions on Very Large Scale Integration (VLSI) Systems)
巻:
25
号:
3
ページ:
844-856
発行年:
2017年
JST資料番号:
W0516A
ISSN:
1063-8210
CODEN:
ITCOB4
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)