文献
J-GLOBAL ID:201702211204134994
整理番号:17A1023922
三次元エッジ終端設計とR_ON,sp-N型上部層を持つ700V三重RESURF LDMOSのBVモデル【Powered by NICT】
3-D Edge Termination Design and ${R}_{ ¥mathrm{¥scriptscriptstyle ON},¥text {sp}}$ -BV Model of A 700-V Triple RESURF LDMOS With N-Type Top Layer
著者 (7件):
Qiao Ming
(State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China)
,
Wang Zhengkang
(State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China)
,
Wang Yuru
(Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong)
,
Yu Liangliang
(State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China)
,
Xiao Qianqian
(State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China)
,
Li Zhaoji
(State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China)
,
Zhang Bo
(State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China)
資料名:
IEEE Transactions on Electron Devices
(IEEE Transactions on Electron Devices)
巻:
64
号:
6
ページ:
2579-2586
発行年:
2017年
JST資料番号:
C0222A
ISSN:
0018-9383
CODEN:
IETDAI
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)