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J-GLOBAL ID:201702217963614266
整理番号:17A1833429
ゲート-ドレインアンダーラップを有する二重ゲートトンネルFETのためのコンパクトモデル【Powered by NICT】
Compact Model for Double-Gate Tunnel FETs With Gate-Drain Underlap
著者 (5件):
Xu Peng
(Shenzhen Key Laboratory of Advanced Electron Device and Integration, School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School, Shenzhen, China)
,
Lou Haijun
(Shenzhen Key Laboratory of Advanced Electron Device and Integration, School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School, Shenzhen, China)
,
Zhang Lining
(College of Electronic Science and Technology, Shenzhen University, Shenzhen, China)
,
Yu Zhonghua
(Shenzhen Key Laboratory of Advanced Electron Device and Integration, School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School, Shenzhen, China)
,
Lin Xinnan
(Shenzhen Key Laboratory of Advanced Electron Device and Integration, School of Electronic and Computer Engineering, Peking University Shenzhen Graduate School, Shenzhen, China)
資料名:
IEEE Transactions on Electron Devices
(IEEE Transactions on Electron Devices)
巻:
64
号:
12
ページ:
5242-5248
発行年:
2017年
JST資料番号:
C0222A
ISSN:
0018-9383
CODEN:
IETDAI
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)