文献
J-GLOBAL ID:201702221145540683
整理番号:17A1567958
固有コア冗長性を利用した変動を意識した信頼性のあるメニーコアシステムの設計【Powered by NICT】
Variation-Aware Reliable Many-Core System Design by Exploiting Inherent Core Redundancy
著者 (5件):
Li Huai-Ting
(Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan)
,
Chou Ching-Yao
(Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan)
,
Hsieh Yuan-Ting
(Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan)
,
Chu Wei-Ching
(Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan)
,
Wu An-Yeu
(Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan)
資料名:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
(IEEE Transactions on Very Large Scale Integration (VLSI) Systems)
巻:
25
号:
10
ページ:
2803-2816
発行年:
2017年
JST資料番号:
W0516A
ISSN:
1063-8210
CODEN:
ITCOB4
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)