文献
J-GLOBAL ID:201702224824373030
整理番号:17A0855287
降圧パターン形成とダミーゲートプロセスを用いたナノスケールトライゲート電界効果トランジスタの作製【Powered by NICT】
Fabrication of a nano-scaled tri-gate field effect transistor using the step-down patterning and dummy gate processes
著者 (4件):
Lee Jae Ho
(Department of Materials Science and Engineering, Inter-University Semiconductor Research Center, Seoul National University, Gwanak-ro 1, Daehag-dong, Gwanak-gu, Seoul 151-744, Republic of Korea)
,
Kim Dong-Gun
(Department of Materials Science and Engineering, Inter-University Semiconductor Research Center, Seoul National University, Gwanak-ro 1, Daehag-dong, Gwanak-gu, Seoul 151-744, Republic of Korea)
,
Lee Hyun-Jae
(Department of Materials Science and Engineering, Inter-University Semiconductor Research Center, Seoul National University, Gwanak-ro 1, Daehag-dong, Gwanak-gu, Seoul 151-744, Republic of Korea)
,
Hwang Cheol Seong
(Department of Materials Science and Engineering, Inter-University Semiconductor Research Center, Seoul National University, Gwanak-ro 1, Daehag-dong, Gwanak-gu, Seoul 151-744, Republic of Korea)
資料名:
Microelectronic Engineering
(Microelectronic Engineering)
巻:
173
ページ:
33-41
発行年:
2017年
JST資料番号:
C0406B
ISSN:
0167-9317
CODEN:
MIENEF
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
オランダ (NLD)
言語:
英語 (EN)