文献
J-GLOBAL ID:201702229512241722
整理番号:17A1641298
論理構造還元方式に基づく低電力19トランジスタ真の単相クロックフリップフロップの設計【Powered by NICT】
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes
著者 (5件):
Lin Jin-Fa
(Department of Information and Communication Engineering, Chaoyang University of Technology, Taichung, Taiwan)
,
Sheu Ming-Hwa
(Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu, Taiwan)
,
Hwang Yin-Tsung
(Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan)
,
Wong Chen-Syuan
(Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu, Taiwan)
,
Tsai Ming-Yan
(Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu, Taiwan)
資料名:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
(IEEE Transactions on Very Large Scale Integration (VLSI) Systems)
巻:
25
号:
11
ページ:
3033-3044
発行年:
2017年
JST資料番号:
W0516A
ISSN:
1063-8210
CODEN:
ITCOB4
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)