文献
J-GLOBAL ID:201702231930634932
整理番号:17A1635320
多層相互接続構造を有する薄膜トランジスタベースの擬CMOS論理アレイのための設計方法論【Powered by NICT】
Design methodology for thin-film transistor based pseudo-CMOS logic array with multi-layer interconnect architecture
著者 (7件):
Qinghang Zhao
(Tsinghua National Laboratory for Information Science and Technology, Department of Electronic Engineering, Tsinghua University, Beijing, China)
,
Yongpan Liu
(Tsinghua National Laboratory for Information Science and Technology, Department of Electronic Engineering, Tsinghua University, Beijing, China)
,
Wenyu Sun
(Tsinghua National Laboratory for Information Science and Technology, Department of Electronic Engineering, Tsinghua University, Beijing, China)
,
Jiaqing Zhao
(Department of Electronic Engineering, Shanghai Jiao Tong University, China)
,
Hailong Yao
(Tsinghua National Laboratory for Information Science and Technology, Department of Electronic Engineering, Tsinghua University, Beijing, China)
,
Xiaojun Guo
(Department of Electronic Engineering, Shanghai Jiao Tong University, China)
,
Huazhong Yang
(Tsinghua National Laboratory for Information Science and Technology, Department of Electronic Engineering, Tsinghua University, Beijing, China)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2017
号:
DAC
ページ:
1-6
発行年:
2017年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)