文献
J-GLOBAL ID:201702233169183691
整理番号:17A0020885
擬似CMOS回路のための雑音余裕解析【Powered by NICT】
Noise margin analysis for Pseudo-CMOS circuits
著者 (6件):
Zhao Qinghang
(Department of Electronic Engineering Tsinghua University Beijing, China)
,
Sun Wenyu
(Department of Electronic Engineering Tsinghua University Beijing, China)
,
Liu Yongpan
(Department of Electronic Engineering Tsinghua University Beijing, China)
,
Yang Huazhong
(Department of Electronic Engineering Tsinghua University Beijing, China)
,
Zhao Jiaqing
(Department of Electronic Engineering Shanghai Jiaotong University Shanghai, China)
,
Guo Xiaojun
(Department of Electronic Engineering Shanghai Jiaotong University Shanghai, China)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2016
号:
CAD-TFT
ページ:
1
発行年:
2016年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)