文献
J-GLOBAL ID:201702238883397050
整理番号:17A1568148
準閾値動作に対する予荷電局所ビットライン共用SRAMアーキテクチャ【Powered by NICT】
Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation
著者 (4件):
Oh Tae Woo
(School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea)
,
Jeong Hanwool
(School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea)
,
Park Juhyun
(School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea)
,
Jung Seong-Ook
(School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea)
資料名:
IEEE Transactions on Circuits and Systems 1: Regular Papers
(IEEE Transactions on Circuits and Systems 1: Regular Papers)
巻:
64
号:
10
ページ:
2737-2747
発行年:
2017年
JST資料番号:
C0226B
ISSN:
1549-8328
CODEN:
ITCSCH
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)