文献
J-GLOBAL ID:201702241538824263
整理番号:17A1729857
ULPビットセルとオンチップ適応逆バイアス発生を伴う28fJ/bitアクセスエネルギーを達成する28nm FDSOIにおける80MHz0.4V ULV SRAMマクロ【Powered by NICT】
An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation
著者 (6件):
Haine Thomas
(ICTEAM Institute, Electronic Circuits and Systems (ECS), Universite ́ catholique de Louvain, Louvain-la-Neuve, Belgium)
,
Nguyen Quoc-Khoi
(ICTEAM Institute, Electronic Circuits and Systems (ECS), Universite ́ catholique de Louvain, Louvain-la-Neuve, Belgium)
,
Stas Francois
(ICTEAM Institute, Electronic Circuits and Systems (ECS), Universite ́ catholique de Louvain, Louvain-la-Neuve, Belgium)
,
Moreau Ludovic
(ICTEAM Institute, Electronic Circuits and Systems (ECS), Universite ́ catholique de Louvain, Louvain-la-Neuve, Belgium)
,
Flandre Denis
(ICTEAM Institute, Electronic Circuits and Systems (ECS), Universite ́ catholique de Louvain, Louvain-la-Neuve, Belgium)
,
Bol David
(ICTEAM Institute, Electronic Circuits and Systems (ECS), Universite ́ catholique de Louvain, Louvain-la-Neuve, Belgium)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2017
号:
ESSCIRC
ページ:
312-315
発行年:
2017年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)