文献
J-GLOBAL ID:201702242788584415
整理番号:17A0417623
コンパクト9F21T1MTJ細胞と階層ビット線アーキテクチャを用いた23.5A4Gb LPDDR2STT-MRAM【Powered by NICT】
23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture
著者 (17件):
Rho Kwangmyoung
(SK hynix Semiconductor, Icheon, Korea)
,
Tsuchida Kenji
(Toshiba Electronics Korea, Seoul, Korea)
,
Kim Dongkeun
(SK hynix Semiconductor, Icheon, Korea)
,
Shirai Yutaka
(Toshiba Electronics Korea, Seoul, Korea)
,
Bae Jihyae
(SK hynix Semiconductor, Icheon, Korea)
,
Inaba Tsuneo
(Toshiba Electronics Korea, Seoul, Korea)
,
Noro Hiromi
(Toshiba Electronics Korea, Seoul, Korea)
,
Moon Hyunin
(SK hynix Semiconductor, Icheon, Korea)
,
Chung Sungwoong
(SK hynix Semiconductor, Icheon, Korea)
,
Sunouchi Kazumasa
(Toshiba Electronics Korea, Seoul, Korea)
,
Park Jinwon
(SK hynix Semiconductor, Icheon, Korea)
,
Park Kiseon
(SK hynix Semiconductor, Icheon, Korea)
,
Yamamoto Akihito
(Toshiba Electronics Korea, Seoul, Korea)
,
Chung Seoungju
(SK hynix Semiconductor, Icheon, Korea)
,
Kim Hyeongon
(SK hynix Semiconductor, Icheon, Korea)
,
Oyamatsu Hisato
(Toshiba Electronics Korea, Seoul, Korea)
,
Oh Jonghoon
(SK hynix Semiconductor, Icheon, Korea)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2017
号:
ISSCC
ページ:
396-397
発行年:
2017年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)