文献
J-GLOBAL ID:201702246147142851
整理番号:17A0852237
MBレベル設計のための3D垂直RRAMアレイアーキテクチャの準解析的モデル【Powered by NICT】
Quasi-Analytical Model of 3-D Vertical-RRAM Array Architecture for MB-Level Design
著者 (6件):
Li Zhiwei
(College of Electronic Science and Engineering, National University of Defense Technology, Changsha, China)
,
Chen Pai-Yu
(School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA)
,
Liu Haijun
(College of Electronic Science and Engineering, National University of Defense Technology, Changsha, China)
,
Li Qingjiang
(College of Electronic Science and Engineering, National University of Defense Technology, Changsha, China)
,
Xu Hui
(College of Electronic Science and Engineering, National University of Defense Technology, Changsha, China)
,
Yu Shimeng
(School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA)
資料名:
IEEE Transactions on Electron Devices
(IEEE Transactions on Electron Devices)
巻:
64
号:
4
ページ:
1568-1574
発行年:
2017年
JST資料番号:
C0222A
ISSN:
0018-9383
CODEN:
IETDAI
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)