文献
J-GLOBAL ID:201702247022530934
整理番号:17A0279042
FPGAを用いたハードウェア効率のよい故障許容星状細胞神経回路網【Powered by NICT】
An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network
著者 (9件):
Johnson Anju P.
(Department of Electronics, University of York, YO10 5DD, UK)
,
Halliday David M.
(Department of Electronics, University of York, YO10 5DD, UK)
,
Millard Alan G.
(Department of Electronics, University of York, YO10 5DD, UK)
,
Tyrrell Andy M.
(Department of Electronics, University of York, YO10 5DD, UK)
,
Timmis Jon
(Department of Electronics, University of York, YO10 5DD, UK)
,
Liu Junxiu
(School of Computing and Intelligent Systems, Ulster University, Derry BT48 7JL, UK)
,
Harkin Jim
(School of Computing and Intelligent Systems, Ulster University, Derry BT48 7JL, UK)
,
McDaid Liam
(School of Computing and Intelligent Systems, Ulster University, Derry BT48 7JL, UK)
,
Karim Shvan
(School of Computing and Intelligent Systems, Ulster University, Derry BT48 7JL, UK)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2016
号:
SSCI
ページ:
1-8
発行年:
2016年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)