文献
J-GLOBAL ID:201702248283519712
整理番号:17A0085402
抵抗変化型スイッチング電子シナプスによる確率論的グラフモデルを訓練する
Training a Probabilistic Graphical Model With Resistive Switching Electronic Synapses
著者 (9件):
Eryilmaz Sukru Burc
(Electrical Engineering Department, Stanford University, Stanford, CA, USA)
,
Neftci Emre
(Department of Cognitive Sciences, University of California at Irvine, Irvine, CA, USA)
,
Joshi Siddharth
(Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA, USA)
,
Kim SangBum
(IBM Research, Yorktown Heights, NY, USA)
,
BrightSky Matthew
(IBM Research, Yorktown Heights, NY, USA)
,
Lung Hsiang-Lan
(Emerging Central Lab., Macronix International Co., Ltd., Hsinchu Science Park, Taiwan)
,
Lam Chung
(IBM Research, Yorktown Heights, NY, USA)
,
Cauwenberghs Gert
(Department of Bioengineering, University of California at San Diego, San Diego, CA, USA)
,
Wong Hon-Sum Philip
(Electrical Engineering Department, Stanford University, Stanford, CA, USA)
資料名:
IEEE Transactions on Electron Devices
(IEEE Transactions on Electron Devices)
巻:
63
号:
12
ページ:
5004-5011
発行年:
2016年
JST資料番号:
C0222A
ISSN:
0018-9383
CODEN:
IETDAI
資料種別:
逐次刊行物 (A)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)