文献
J-GLOBAL ID:201702257620444831
整理番号:17A0417485
空間-時間画像処理のための三次元積層140GOPSカラム並列PEと4.9A1ms高速ビジョンチップ【Powered by NICT】
4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing
著者 (15件):
Yamazaki Tomohiro
(Sony Semiconductor Solutions, Atsugi, Japan)
,
Katayama Hironobu
(Sony Semiconductor Solutions, Atsugi, Japan)
,
Uehara Shuji
(Sony Semiconductor Solutions, Atsugi, Japan)
,
Nose Atsushi
(Sony Semiconductor Solutions, Atsugi, Japan)
,
Kobayashi Masatsugu
(Sony Semiconductor Solutions, Atsugi, Japan)
,
Shida Sayaka
(Sony Semiconductor Solutions, Atsugi, Japan)
,
Odahara Masaki
(Sony LSI Design, Atsugi, Japan)
,
Takamiya Kenichi
(Sony LSI Design, Atsugi, Japan)
,
Hisamatsu Yasuaki
(Sony LSI Design, Atsugi, Japan)
,
Matsumoto Shizunori
(Sony LSI Design, Atsugi, Japan)
,
Miyashita Leo
(University of Tokyo, Bunkyo, Japan)
,
Watanabe Yoshihiro
(University of Tokyo, Bunkyo, Japan)
,
Izawa Takashi
(Sony Semiconductor Solutions, Atsugi, Japan)
,
Muramatsu Yoshinori
(Sony Semiconductor Solutions, Atsugi, Japan)
,
Ishikawa Masatoshi
(University of Tokyo, Bunkyo, Japan)
資料名:
IEEE Conference Proceedings
(IEEE Conference Proceedings)
巻:
2017
号:
ISSCC
ページ:
82-83
発行年:
2017年
JST資料番号:
W2441A
資料種別:
会議録 (C)
記事区分:
原著論文
発行国:
アメリカ合衆国 (USA)
言語:
英語 (EN)